This is a fresh start at a blog about Verilog! The goal of this blog is to provide insightful tips and tricks to those grappling with digital design in both Verilog and SystemVerilog. I also plan to make posts about interesting projects I am working on or discoveries I make.
I (currently) a senior in Electrical and Computer Engineering at Carnegie Mellon University with a focus in digital logic design. I have taken several courses with projects written in Verilog and SystemVerilog including:
18-240: Structure and Design of Digital Systems
18-341: Logic Design Using Simulation, Synthesis, and Verification Techniques
18-340: Digital Computation
18-447: Introduction to Computer Architecture
My projects for these classes include the Mastermind game for the Spartan 3 FPGA, a gate-level implementation of a 32-bit IEEE floating-point unit, a partial USB 2.0 device controller, and a MIPS architecture. For Build18, a student-run ECE-project organization at CMU, I plan to help design a game of tetris which will run on the Xilinx Virtex-V FPGA and will use a PS/2 keyboard and supply VGA output.
In addition, this spring will be my second semester working as a teaching assistant for 18-240. Students of this class in particular may find the contents of this to be helpful – at least that is my hope :)
latchesinferred 